Develop a hypothetical architecture with illustrative instruction and data formats

1. Conduct research on IEEE, ACM or other relevant publications about the computer technology history as well as developments and o submit seven different major quotes since 1950s for each decade and itemize seven important milestones since 1940s (other than ones covered during the lectures). (Also, submit all original complete reference information) o study six early computer systems in terms of architectural and organizational perspectives, submit their pictures (with complete reference info), compare with a particular current computer system, and discuss potential anticipated computer systems in the year-2031. o briefly explain the following concepts: Neuromorphic computing, Zettascale computing, Quantum computing, Nanocomputing, Edge computing, Colossus (related to the computer architecture field), Probabilistic computing, Cloud computing, Virtualized instruction set architecture, Sniper Multi-core simulator.

2. Develop a hypothetical architecture with illustrative instruction and data formats, instruction sets, etc., explain the instruction and machine cycles step-by-step by developing a short program (at least, with three arithmetic operations, two logic operations, two memory or three I/O operations) and by indicating the corresponding register operations. All architectural, etc., selections must to be justified sufficiently.

3. Conduct research on the IEEE or ACM journal articles or conference proceedings, published within the last one-year period, about the memory concepts. Submit a total of three-page summary for three important publications (along with the original paper complete reference information only) on different cache memory aspects.

4. Develop a hypothetical architecture with illustrative instruction and data formats, instruction sets, etc., and a short program (at least, with six data entry from keyboard, data storage to two memory locations, and the “average” value calculation of the data entered from the keyboard) to compare the three cache mapping algorithms. Indicate the corresponding run-time register contents and justify all architectural, etc., selections sufficiently